verilog

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I wrote this code in Verilog and there are no error messages, but it doesn't work
user_190927690
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1
1
74
quartus modelsim system-verilog hdl verilog
How to assign "all the last bits" automatically in Verilog
user_88497550
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1
2
57
verilog
Getting output of convolutional PE as XXX instead of a number?
user_174085850
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1
1
671
test-bench system-verilog verilog
Why am I getting the error : part select cannot be applied to scalar in my testbench?
user_188614030
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1
2
364
test-bench system-verilog verilog
predict clock in user defined primitive
user_142641770
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1
1
45
system-verilog verilog
Why do I get "Module port is neither input nor output" for all wires?
user_187038700
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1
1
84
yosys verilog
Masking input unpacked array
user_45059980
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1
2
71
system-verilog verilog
Why is it wrong when I separately assign the output values?
user_185405510
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1
1
102
verilog
Illegal output or inout port connection for port 'next_key'
user_181957970
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1
1
54
verilog
Why do I keep getting this "syntax error binary base error" in EDA playground?
user_183282290
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1
2
105
verilog
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