Why do I keep getting this "syntax error binary base error" in EDA playground?

user_18328229 0
Viewed 105

I tried several things, but I keep getting this error in EDA playground. How do I fix it? I'm trying to implement a system to add, subtract, etc., and get flags for ADDS and SUBS. I tried creating a reg variable and then assigning the flags to that, but that didn't work. The code runs when I don't use any flags in my case statements. Here is my code and the error below:

module alu(A,B, ALU_Sel,ALU_Out,Carry,Zero,Overflow,Negative,ALU_Result);
  
  input wire[63:0] A,B;  // ALU 64-bit Inputs                 
  input wire [3:0] ALU_Sel;// ALU Selection
  reg C;
  reg Z;
  reg O;
  reg N;
  output reg [63:0] ALU_Out; // ALU 8-bit Output
  output reg Carry; // Carry Out Flag
  output reg Zero;
  output reg Overflow;
  output reg Negative;
  output reg [63:0] ALU_Result;
  
    assign ALU_Out = ALU_Result; // ALU out
  assign Carry=C;
  assign Zero = Z;
  assign Overflow = O;
  asssign Negative = N;
     always @(*)
    begin
      Carry=0;
      Zero=0;
      Overflow=0;
      Negative=0;
      
      case(ALU_Sel[3:0])
          4'b0000:  //AND -h0
          ALU_Result = A & B;
          C=1;
          
          4'b0010: //ADD -h2
          ALU_Result = A + B;
          
          4'b0011: //ADDS -h3
          ALU_Result = A + B;
          //CREATE FLAGS HERE
          //reg Carry = 1;
          
          4'b1100: //EOR -h12
          ALU_Result =A^B;
          
          4'b0110: //SUB -h6
          ALU_Result = A-B;
          
          4'b0111: //SUBS -h7
          ALU_Result = A-B;
          //CREATE FLAGS HERE
          
          4'b1001: //LSL -h9
          ALU_Result = A << B;
          
          4'b0001: //OR -h1
          ALU_Result = A | B;
          
         endcase
      end
endmodule

ERROR VCP2000 "Syntax error. Unexpected token: =." "design.sv" 20  21
ERROR VCP2000 "Syntax error. Unexpected token: =." "design.sv" 31  13
ERROR VCP2000 "Syntax error. Unexpected token: 4'b0011[_BINARY_BASE]." "design.sv" 36  18
ERROR VCP2000 "Syntax error. Unexpected token: 4'b1100[_BINARY_BASE]." "design.sv" 41  18
ERROR VCP2000 "Syntax error. Unexpected token: 4'b0110[_BINARY_BASE]." "design.sv" 44  18
ERROR VCP2000 "Syntax error. Unexpected token: 4'b0111[_BINARY_BASE]." "design.sv" 47  18
ERROR VCP2000 "Syntax error. Unexpected token: 4'b1001[_BINARY_BASE]." "design.sv" 51  18
ERROR VCP2000 "Syntax error. Unexpected token: 4'b0001[_BINARY_BASE]." "design.sv" 54  18
verilog
2 Answers

You are missing bracketing begin/end keywords around each case branch item.

module alu(
  input wire[63:0] A,B,  // ALU 64-bit Inputs                 
  input wire [3:0] ALU_Sel,// ALU Selection
  output reg [63:0] ALU_Out, // ALU 8-bit Output
  output reg Carry, // Carry Out Flag
  output reg Zero,
  output reg Overflow,
  output reg Negative,
  output reg [63:0] ALU_Result
);
  
always @(*)
    begin
      Carry=0;
      Zero=0;
      Overflow=0;
      Negative=0; 
      case(ALU_Sel[3:0])
          4'b0000:  begin //AND -h0
          ALU_Result = A & B;
          Carry=1;
          end
          4'b0010: begin //ADD -h2
          ALU_Result = A + B;
          end
          4'b0011: begin //ADDS -h3
          ALU_Result = A + B;
          //CREATE FLAGS HERE
          //reg Carry = 1;
          end
          4'b1100: begin//EOR -h12
          ALU_Result =A^B;
          end
          4'b0110: begin //SUB -h6
          ALU_Result = A-B;
          end
          4'b0111: begin//SUBS -h7
          ALU_Result = A-B;
          //CREATE FLAGS HERE
          end
          4'b1001: begin //LSL -h9
          ALU_Result = A << B;
          end
          4'b0001: begin//OR -h1
          ALU_Result = A | B;
          end
         endcase
      end
endmodule
user_27556070

You have several errors in your code.

The 1st error you see on EDAplayground is on line 20 (using the Adlec simulator), which is this line:

  asssign Negative = N;

In my web browser, EDAplayground applies syntax highlighting to the code, where Verilog keywords are colored and other works are in black print. This shows the asssign word as black, which means it does not recognize it as a Verilog keyword. It is a typo; change it to:

  assign Negative = N;

The next error is this line:

      Carry=1;

On its own, the syntax is fine, but taken together with the line above it, there is an error. When multiple statements are used inside a case statement, they must be enclosed by the begin/end keywords.

      4'b0000:  //AND -h0
      begin
          ALU_Result = A & B;
          C=1;
      end

After making the above changes, there are still errors. You make multiple assignments to the same signal (Carry): one using the assign statement, and another inside the always block. You can't do both, which means you need to decide which is the one you want. Deleting the assign statements would remove all the errors from your code.

Judging by your comments ("//CREATE FLAGS HERE"), I assume you are not yet finished with the design. For example, the Z signal is not assigned a value.

user_1977580
Related