Masking input unpacked array

user_4505998 0
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I want to "mask" an input unpacked array given a specific signal. If that signal is 1, I want the input to be all zeroes instead of the given array.

module thing (
  input clk,
  input rst,
  input packedBits[`PB_SIZE]
);
// ...
endmodule

module top (
  input clk,
  input rst
);

  logic packedBits[`PB_SIZE];

  mod_i thing (
    .clk(clk),
    .rst(rst),
    // I can manually put `PB_SIZE zeroes, but I want the compiler to do it for me
    .packedBits(rst ? {0,...,0} : packedBits)
  )
endmodule

Putting just {0,0,0,0} when `PB_SIZE is 4 works, but how could I do it in a more generic way?

system-verilog verilog
2 Answers

You can use the replication operator:

.packedBits(rst ? '{`PB_SIZE{0}} : packedBits)

Refer to IEEE Std 1800-2017, section 5.11 Array literals.

Here is a complete example on EDA playground. It runs on Cadence and Synopsys, but there are errors on Mentor. It seems Mentor does not support this syntax yet.

Simulators sometimes struggle with complex expressions connected to module ports. It is usually a good idea to simplify the connection using a separate signal.

`define PB_SIZE 5

module thing (input packedBits [`PB_SIZE]);
    initial #1 $display("%m %p", packedBits);
endmodule

module tb;
    bit rst = 1;
    logic packedBits      [`PB_SIZE];
    logic packedBitsGated [`PB_SIZE] = rst ? '{`PB_SIZE{0}} : packedBits;

    thing mod_i (.packedBits(packedBitsGated));

    initial begin
        packedBits = '{`PB_SIZE{1}};
        #1 $display("%m %p", packedBits);
    end
endmodule

This works on all 3 simulators on EDA playground.

user_1977580

You can use a default in an assignment patterns. Then there is no need to know its size.

.packedBits(rst ? '{default:0} : packedBits)
user_27556070
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