How to assign "all the last bits" automatically in Verilog

user_8849755 0
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Consider this

reg [5:0]assign_me;
reg [11:0]source_of_data;

assign_me <= source_of_data[5:0];

where assign_me always gets the least significant bits of source_of_data. Here the 5 is hardcoded in the last line in the sense that if for some reason the definition of assign_me changes to reg [6:0]assign_me I will have to change the last line. Is there any way to avoid this? Like for example in a pythonic notation something like assign_me <= source_of_data[:0]?

verilog
2 Answers

You could use:

assign_me <= source_of_data;

Verilog will assign the LSB's. But, you might get warnings about width mismatch.

A cleaner way is to use a parameter:

parameter WIDTH = 6;
reg [WIDTH-1:0]assign_me;
reg [11:0]source_of_data;

assign_me <= source_of_data[WIDTH-1:0];
user_1977580

When it comes to integral (packed) arrays, Verilog is loosely typed. Verilog will right justify to align LSBs, then make the assignment padding or truncating the MSB. You do not need to select a specific set of bits unless you need to mask bits on either end. Some tools will generate size mismatch warnings, especially around port connections, but the language does not require it.

One thing to be careful of is that selecting bits of a single is always unsigned regardless of the sightedness of the signal as a whole.

user_27556070
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