quartus

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I wrote this code in Verilog and there are no error messages, but it doesn't work
user_190927690
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74
quartus modelsim system-verilog hdl verilog
Verilog HDL syntax error at practice.v(7) near text "or"; expecting ")"
user_177854330
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1
2
237
quartus verilog syntax-error
In Intel Quartus, can I initialize RAM using a string parameter?
user_12875540
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2
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185
quartus intel-fpga system-verilog fpga verilog
Beginner's Question on Compiling Verilog in Quartus
user_165858260
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70
quartus verilog
I want to type conversion in Quartus2 Verilog
user_161669030
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1
1
53
quartus verilog
Can't compile with VHDL 2008 Quartus Prime
user_149008930
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3
2
801
quartus vhdl intel
Does Quartus support in-memory synthesis?
user_116576410
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1
1
49
quartus intel-fpga
What am I doing wrong? Testbench not updating correctly
user_152040470
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1
1
75
quartus intel-fpga fpga verilog
Error: syntax error in set_input_delay (Quartus)
user_116328250
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2
2
120
quartus verilog syntax-error
Where would a GND driver come from?
user_139657960
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2
1
116
quartus system-verilog verilog
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