predict clock in user defined primitive

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So basically there is udp in verilog for which we define tables. This table is maintained in memory in code.

Eg.

primitive abc(q,d,clk,not);
input d, clk, not;
output q;
reg q;

table

    |0 1 ? : ? : 0;|

    |1 1 ? : ? : 1;|

    |0 * ? : 0 : 0;|

    |1 * ? : 1 : 1;|

    |* 0 ? : ? : -;|

    |? ? * : ? : x;|

endtable
endprimitive

My question is can we predict which input in udp is clock just from the transition table (NOTE : question only for sequential udp)?

system-verilog verilog
1 Answers

Yes you can and tools do this—you cannot rely on the signal names to infer functionality.

The key line that shows you which is the clock/enable for a level sensitive sequencial udp is the no change line:

* 0 ? : ? : -;

This works for a level sensitivity UDPs, but doing this generically for all possible truth tables could get very complicated. You can certainly eliminate entries with the output going to X.

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