verilog

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Does defining a vector before a single bit input affect the single bit?
user_191858160
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42
system-verilog verilog
Use testbench to check module but output does not change when I use other input
user_113467350
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33
test-bench verilog
SystemVerilog: Aggregate class with array of class objects
user_111276230
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49
test-bench system-verilog hdl verilog oop
Why is this counter assignment wrong?
user_199704300
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52
system-verilog verilog
Set a variable number of bits in a signal
user_199571450
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1
2
46
verilog
Truncated signed Fixed point conversion from Q2.28 to Q2.14 in verilog
user_32782960
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1
48
verilog fixed-point
Read each character from file and store in array
user_193883190
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1
1
69
system-verilog verilog fgets scanf
How can I write Verilog code for an 8x1 mux using 2x1 mux?
user_161478700
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1
1
55
verilog
Wire assignment inside IF block
user_103580170
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2
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63
system-verilog verilog
How to get more info in testbench results?
user_198059480
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42
verilog
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