verilog

212 Questions
Newest Active Unanswered Frequent
Score
View
Card Compact
Why is my output empty in program counter with mux adder flopper?
user_174100560
•
1
1
40
verilog
Verilog inout port assignment results in X
user_115653640
•
1
1
252
vivado verilog
Function in verilog
user_144256790
•
1
1
133
verilog
EDAPlayground: Verilog code "reached maximum runtime"
user_143107350
•
2
1
209
system-verilog infinite-loop verilog
Beginner's Question on Compiling Verilog in Quartus
user_165858260
•
1
1
70
quartus verilog
localparameters to make code generic to support different data widths
user_25322960
•
2
2
128
fpga hdl verilog
Case statement doesn't seem to be working
user_158315220
•
1
1
42
verilog switch-statement
Module that converts index to a value: syntax error near text "="; expecting ".", or "("
user_158315220
•
1
1
95
verilog
Behavioral designing of a multiple input and gate
user_171726990
•
2
1
125
system-verilog verilog logical-operators
8-bit select Adder with 4-bit adder result is xxxxxxx
user_158264490
•
1
1
227
verilog
Hot Questions