Why is my output empty in program counter with mux adder flopper?

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Whenever I run this code, the output is empty, like no output at end of result. Output from a counter not showing as initialized in Verilog simulation.

And every single code working with testbench except program counter every time I run this, the output is empty. Please help me to fix the code.

module Program_counter(clk, reset, PC_sel, Ext_imm, PC);
input wire clk, reset, PC_sel;
input wire [31:0] Ext_imm;
inout [31:0] PC; 
reg [31:0] PC;   
wire [31:0] PC_Next, PC_4, PC_Target;

floper#(32) PCreg(clk, resest, PC_Next, PC);
adder PCplus4(PC, 32'd4, PC_4);
adder PCtarget(PC, Ext_imm, PC_Target);
mux#(32) PCmux(PC_4, PC_Target, PC_sel, PC_Next);
endmodule


module TB_PC();
reg clk, reset, PC_sel;
reg [31:0] Ext_imm;
wire [31:0] PC;

Program_counter testbench(clk, reset, PC_sel, Ext_imm, PC);
always #5clk=~clk;

initial
begin
 clk=0;
 reset=0;
 PC_sel=0;
 #20
 reset=1;
 #20
 PC_sel=1;
 Ext_imm=32'h0000003A;
 #10
 PC_sel=1;
 Ext_imm=32'h00000B3A;
 PC_sel=0;
 Ext_imm=32'h0000DB3A;
end
endmodule

module adder(input [31:0] a, b,
 output [31:0] y);
 assign y = a + b;
endmodule

module floper#(parameter WIDTH = 8)
              (input wire   CLK, reset,
               input wire   [WIDTH-1:0] d,
               output reg [WIDTH-1:0] q);
              

always@(posedge CLK, posedge reset)
 if (reset)
  q <= 0;
 else
  q <= d;
endmodule

module mux#(parameter WIDTH = 8)
           (input wire [WIDTH-1:0] d0, d1,
            input wire s,
            output reg [WIDTH-1:0] y);

assign y= s ? d1 : d0;
endmodule
verilog
1 Answers

Perhaps the simulator you used did not give you any errors or warnings. If you use simulators on edaplayground, you will get helpful messages.

inout [31:0] PC; 
              |
xmvlog: *E,SVNVAR: Variable 'PC', declared in a module/macromodule, cannot also be declared inout.

One way to avoid that syntax error is to comment out (or delete) the reg line:

//reg [31:0] PC;

I also get this warning:

floper#(32) PCreg(clk, resest, PC_Next, PC);
                            |
xmelab: *W,CSINFI: implicit wire has no fanin (TB_PC.testbench.resest).

To fix that typo, change:

floper#(32) PCreg(clk, resest, PC_Next, PC);

to:

floper#(32) PCreg(clk, reset, PC_Next, PC);

After those 2 changes, the PC output is no longer unknown (x).

user_1977580
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