Module that converts index to a value: syntax error near text "="; expecting ".", or "("

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This module is supposed to convert the index value iState into the corresponding value in the array sequence and return it as oV. However, I get this error at oV = sequence[iState]; when I run it:

Error (10170): Verilog HDL syntax error at assign32498071.v(70) near text "="; expecting ".", or "("

module StateToCountSequence(iState, oV);
    //declare the input and output 
    input iState;
    output [3:0]oV;
  
    //declare any internal wire and reg types here.
    reg [3:0]sequence[14:0];
    
    initial begin
        sequence[0] = 4'd3;
        sequence[1] = 4'd2;
        sequence[2] = 4'd4;
        sequence[3] = 4'd9;
        sequence[4] = 4'd9;
        sequence[5] = 4'd0;
        sequence[6] = 4'd7;
        sequence[7] = 4'd1;
        sequence[8] = 4'd1;
        sequence[9] = 4'd5;
        sequence[10] = 4'd1;
        sequence[11] = 4'd7;
        sequence[12] = 4'd0;
        sequence[13] = 4'd8;
        sequence[14] = 4'd9;
    end

    oV = sequence[iState];
endmodule

Does anyone know what I should do about this?

verilog
1 Answers

You are missing the assign keyword for your continuous assignment to oV. Change:

oV = sequence[iState];

to:

assign oV = sequence[iState];

That fixes the compile error.

It is strange that your index signal (iState) is a 1-bit signal, which means it can only take on the known values 0 and 1. Thus, you can only access sequence [0] and [1].

Note that sequence is a SystemVerilog keyword, which means that it can not be used as a signal name if SV features are enabled with your tools. I recommend changing the name to something else.

user_1977580
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