8-bit select Adder with 4-bit adder result is xxxxxxx

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I'm making an 8-bit selectAdd8 with 4-bit Adder.

There was no complie error, but the result is just xxxxxxxx.

I guess there is some problem with my code, but I can't figure it out.

This is '8bit Select Adder Code'


module selectAdd8(
    input [7:0] a,
    input [7:0] b,
    input cin,
    output reg [7:0] sum,
    output reg cout
    );
        
        reg coutL, sumL, sum0, sum1, cout0, cout1;

        add4 add_lower(a[3:0],b[3:0],cin,sum,cout);
        add4 add4_0(a[7:4],b[7:4],0,sum0,cout0);
        add4 add4_1(a[7:4],b[7:4],1,sum1,cout1);
        
        always @ (*)
        
        if (coutL==1) begin
                sum = {sum1, sumL};
                cout = 1;
        end else begin
                sum = {sum0, sumL};
                cout = 0;
        end
        
endmodule

And this is 4-bit adder code. I've tested this 4-bit adder, and there was no problem.

module add4(
    input [3:0] a,
    input [3:0] b,
    input cin,
    output [3:0] sum,
    output cout
    );
     
assign {cout, sum} = a+b+cin;

endmodule

This is my test code. When I see the result, input is okay, but cout and Sum both are just x and XXXXXXXX.

module selectAdd8_test;

    // Inputs
    reg [7:0] a;
    reg [7:0] b;
    reg cin;

    // Outputs
    wire [7:0] sum;
    wire cout;

    // Instantiate the Unit Under Test (UUT)
    selectAdd8 uut (
        .a(a), 
        .b(b), 
        .cin(cin), 
        .sum(sum), 
        .cout(cout)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;
        cin = 0;
        #100;
        a = 255;
        b = 1;
        cin = 0;
        #100;
        a = 135;
        b = 45;
        cin = 1;
        #100;
        a = 7;
        b = 47;
        cin = 0;
        #100;
        a = 7;
        b = 28;
        cin = 0;
        #100;
        a = 120;
        b = 7;
        cin = 0;
        #100;
        end
      
endmodule

This is the result

verilog
1 Answers

If you are not getting any compile errors or warnings with the code you posted, then you should try different simulators on edaplayground. I see several problems on Cadence, for example, with the selectAdd8 module.

I looked back at your previous Question to try and piece together your intent. sumL and coutL were undriven, so I connected them to the add_lower instance as you had before.

You declared all your sum signals as 1-bit, but they should be 4-bit ([3:0]).

You must declare the internal cout signals as wire, not reg.

Here is code that compiles without errors and simulates without X's:

module selectAdd8(
    input [7:0] a,
    input [7:0] b,
    input cin,
    output reg [7:0] sum,
    output reg cout
    );
        
        wire coutL, cout0, cout1;
        reg [3:0] sumL, sum0, sum1;

  add4 add_lower(a[3:0],b[3:0],cin,sumL,coutL);
  add4 add4_0(a[7:4],b[7:4],1'b0,sum0,cout0);
  add4 add4_1(a[7:4],b[7:4],1'b1,sum1,cout1);
        
        always @ (*)
        
        if (coutL==1) begin
                sum = {sum1, sumL};
                cout = 1;
        end else begin
                sum = {sum0, sumL};
                cout = 0;
        end
        
endmodule
user_1977580
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