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Where would a GND driver come from?
user_139657960
• asked Jul 31, 2020
2
1
116
quartus system-verilog verilog
How to know which simulator is used in cocotb testbench?
user_44229570
• asked Jul 31, 2020
3
1
167
icarus verilator cocotb verilog python
Unable to understand error in D flip flop code
user_115671340
• asked Jul 22, 2020
2
2
115
verilog
SHA-3: Implementation of Theta function according to FIPS-202 not behaving as expected
user_55084970
• asked Jul 16, 2020
2
1
157
sha-3 verilog hash
How to use Arithmetic expression in Enum in system verilog?
user_129371400
• asked Jul 13, 2020
3
1
267
test-bench system-verilog verilog
Verilog Structural description of an Edge-triggered T flip-flop with an synchronous reset (R)
user_62382750
• asked Jul 6, 2020
3
1
415
verilog
Assigning x (dont care) to a register reset value or combinatorical output to improve area efficiency
user_138522600
• asked Jul 2, 2020
3
1
930
system-verilog fpga verilog
Verilog unsigned non-restoring division. Syntax Error: "I give up" Icarus Verilog
user_115202150
• asked Jun 24, 2020
2
2
3010
iverilog verilog
Why is the timer output unknown?
user_134789260
• asked Jun 17, 2020
2
2
84
verilog
What is the difference between these 2 counters?
user_136887250
• asked Jun 16, 2020
2
2
97
system-verilog hdl verilog
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