Unable to understand error in D flip flop code

user_11567134 0
Viewed 115

I have a problem in the test bench code, and I am not getting correct waveforms. Even the clock does not trigger.

CODE for D Flipflop:

module D_FF(o,D,clk);
    
    output reg o;
    input D,clk;
    
    always @ (posedge clk)
        begin
        if(D==1'b1)begin
            o=1'b1;
        end
        else begin
            o=1'b0;
        end
    end
    
endmodule

Code for TestBench:

module DD_flipflop_tb();
    
    reg clk,D;
    wire o;
    
    D_FF i1(o,D,clk);

    initial begin
        clk=1'b0;
        D=1'b0;
    end
    
    always begin
        #20 clk=~clk;
        #35  D=~D;
        #5000 $finish; 
    end
endmodule
verilog
2 Answers

Here is what happens in the always block in your testbench.

At time 0, clk and D are 0.

At time 20, you invert clk, which becomes 1.

At time 55, you invert D, which becomes 1.

At time 5055, you call $finish which terminates the simulation. The statements in the block only execute once, which is why your inputs never change more than once.

In your testbench, initialize them as 0 in an initial block, then separate the clock generation from the data signal.

initial begin
    clk = 0;
    forever #20 clk=~clk;
end

initial begin
   D=0;
   forever #35 D=~D;
end

initial #5000 $finish;
user_1977580

You might want to assign separately the clock and the stimulus in the testbench:

initial begin
  clk = 0;
  D = 0;
  #5000 $finish;
end

//..clock
always
  #20 clk = ~clk;

//..stimulus
always
  #35 D = ~D;
user_129646960
Related