cpu-architecture

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Why do unconditional jumps take up BTB space?
user_458430
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3
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166
branch-prediction cpu-architecture cpu performance
I cannot use "perf_event_open()" with PERF_COUNT_HW_CACHE_LL type
user_36099760
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2
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171
perf amd-processor performancecounter cpu-architecture linux
Would x86 still be fully programmable if it didn't have the Sign Flag (SF)?
user_42997660
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2
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85
masm turing-complete x86 assembly cpu-architecture
Out-of-order execution in C#
Admin1
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3
1
188
compiler-optimization x86-64 assembly cpu-architecture c#
implementing external interrupts in Simple As Possible (SAP) computer with FLAGS registers
user_134778790
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2
0
68
vhdl cpu-architecture
Trouble Understanding Associative Cache
user_136268740
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1
1
46
microprocessors cpu-cache cpu-architecture caching
Why does a loop transitioning from having its uops fed by the Uop Cache to LSD cause a spike in branch-misses?
user_113221310
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4
2
272
micro-architecture branch-prediction x86-64 micro-optimization cpu-architecture
Is logical/arithmetic shift fewer bits faster?
user_156263580
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2
1
166
x86 assembly cpu-architecture c++ performance
Why wasn't DIV instruction implemented to set the CF instead of raising Exceptions
user_69085450
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2
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215
instructions integer-division x86 assembly cpu-architecture
Can't relaxed atomic fetch_add reorder with later loads on x86, like store can?
user_117746080
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4
3
355
stdatomic memory-barriers cpu-architecture multithreading c++
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