cpu-architecture

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Minimum number of input bits required by a circuit to decode
user_12865500
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152
mips assembly cpu-architecture
What happens to the CPU pipeline when the memory with the instructions is changed by another core?
user_333640
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2
2
237
hotpatching pipeline x86 assembly cpu-architecture
Store misses hurt performance?
user_112749330
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2
1
128
cpu-cache cpu-architecture memory-management caching
Atomic operation contention between SMT/HT Threads
user_3098070
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2
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95
compare-and-swap atomic hyperthreading x86 cpu-architecture
Why is clflush an unprivileged instruction in x86?
user_90275410
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2
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116
cpu-cache x86 cpu-architecture
How does Intel's RAPL estimate the power consumption
user_73310610
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3
1
1472
msr energy intel cpu-architecture cpu
Why does my empty loop run twice as fast if called as a function, on Intel Skylake CPUs?
user_52208320
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8
1
223
x86-64 assembly cpu-architecture c performance
bitshift outside allowed range
user_15608500
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3
3
153
undefined-behavior bit-shift assembly cpu-architecture c
What is integer division heavily used for?
user_458430
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8
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153
instructions integer-division division cpu-architecture performance
How does interrupt differ from subroutine calls?
Admin1
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1680
interrupt assembly cpu-architecture
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