cpu-architecture

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What type of input would slow down execution time of dynamic memory allocators malloc() and free()?
user_137499810
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2
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67
dynamic-memory-allocation operating-system real-time cpu-architecture memory-management
(Persistence) ordering of Intel non-temporal stores to the same cache line
user_72896060
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5
1
216
persistent-memory memory-barriers x86 cpu-architecture
Why does FADDP D-form have higher throughput than FADDP Q-form on the Cortex-A72
user_30182430
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2
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188
micro-architecture arm64 neon simd cpu-architecture
Eliding cache snooping for thread-local memory
user_458430
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4
2
101
thread-local operating-system cpu-cache cpu-architecture multithreading
How to explicitly load a structure into L1d cache? Weird results with INVD with CR0.CD = 1 on isolated core with/without hyperthreading
user_140908170
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8
1
323
cpu-cache x86 linux-kernel cpu-architecture c
Undefined symbols for architecture x86_64: "_OBJC_CLASS_$_ASWebAuthenticationSession"
user_146423130
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2
0
1342
visual-studio-app-center onesignal cocoapods cpu-architecture ios
Cache coherency(MESI protocol) between different levels of cache namely L1, L2 and L3
user_56805070
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3
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540
mesi x86-64 cpu-cache cpu-architecture caching
x86_64 Instruction pipelining: Instruction execution order
user_56805070
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2
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125
x86-64 instruction-set assembly cpu-architecture
Manual vectorization using AVX vector intrinsics only runs about the same speed as 4 scalar FP adds on Ryzen?
user_95462170
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5
2
289
avx x86 assembly cpu-architecture c
Why is processing an unsorted array the same speed as processing a sorted array with modern x86-64 clang?
user_7589860
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164
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11318
branch-prediction clang cpu-architecture c++ performance
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