cpu-architecture

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The pipeline execution diagram with or without a delay slot, with predict-taken
user_125527480
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2
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467
mips branch-prediction pipeline assembly cpu-architecture
x86 memory ordering test shows reordering where Intel's manual says there shouldn't be?
user_164820140
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2
1
170
memory-barriers lock-free x86 cpu-architecture c++
Why would the IRET instruction increment EIP by 4?
user_83245850
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2
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94
i386 interrupt x86 cpu-architecture
Initialising global variables in C in Harvard CPU
user_164307980
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2
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128
harvard-architecture global-variables compilation cpu-architecture c
how do we calculate the number of reads/misses of the cache in this code snippet?
user_152331080
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3
1
2000
computer-science cpu-cache cpu-architecture caching
Program counter, fences and processor re-ordering
user_71087690
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2
2
79
memory-barriers x86-64 assembly cpu-architecture windows
Who loads the data of a process into the register bank which is in the data path?
user_159338750
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2
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49
operating-system assembly cpu-architecture
what is the dependency between these variables?
user_152331080
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2
2
100
x86 assembly cpu-architecture
Is valgrind's cachegrind still the go-to tool in 2021?
user_24343480
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5
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200
cachegrind branch-prediction cpu-architecture profiling valgrind
how do i get the cpu information for my computer i.e functional units/latency etc
user_152331080
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3
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203
micro-architecture x86 assembly cpu-architecture
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