Trouble Understanding Associative Cache

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I was reading a book on Cache Optimizations and in the Third Optimization ie Higher Associativity to Reduce Miss Rate The author says

2:1 cache rule (for cache upto size 128KB) A direct-mapped cache of size N has the same miss rate of 2-way associative cache of size N /2.

But the author provides no explanation or proof to this and I am unable to understand this. Could anyone explain how he came up with this rule?

microprocessors cpu-cache cpu-architecture caching
1 Answers

It's a "rule of thumb" that's (apparently) usually true for normal workloads, I'd guess from simulating traces of real workloads like SPECint and/or commercial software. Not an actual law that's always true.

Seems reasonable if most of the misses are just conflict misses, not capacity misses.

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