cpu-architecture

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Should Interlocked.CompareExchange also a volatile variable?
user_625440
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3
3
248
compare-and-swap lock-free volatile cpu-architecture c#
Why different ranges of permitted shift values for ARM LSL vs LSR?
user_98384070
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4
1
652
arm instruction-set assembly cpu-architecture
Understanding micro-architectural causes for longer code to execute 4x faster (AMD Zen 2 architecture)
user_3937560
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4
1
112
amd-processor x86 assembly cpu-architecture c++
Does AVX/AVX2 "exists" on each core?
user_140694910
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3
3
1572
avx avx2 simd cpu-architecture c++
How does Linux handle Intel's Optane Persistent Memory Modules under Memory Mode?
user_41111880
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2
1
404
persistent-memory intel linux-kernel cpu-architecture performance
Why am I seeing more RFO (Read For Ownership) requests using REP MOVSB than with vmovdqa
user_113221310
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6
0
450
memcpy x86-64 micro-optimization intel cpu-architecture
Detect OS x86 or x64, when compiled as x86
user_152326110
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2
1
399
go 32bit-64bit x86 cpu-architecture cross-platform
What is the typical DRAM row buffer size? How to find it?
user_116869130
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2
1
1130
ram cpu-architecture
Do instruction sets like x86 get updated? If so, how is backwards compatibility guaranteed?
Admin1
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2
2
77
instruction-set cpu-architecture
Aarch64 what is late-forwarding?
user_8992550
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6
1
247
arm64 assembly cpu-architecture
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