micro-architecture

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Do memory instructions pass through the load-store queue and issue queue in the microarchitecture
user_106263830
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33
micro-architecture cpu-architecture
handling x86-64 microarchitecture levels in Debian package names
user_120112940
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109
micro-architecture debian-packaging x86-64 debian cpu-architecture
Is prefetch useless if it doesn't complete before load?
user_31549960
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71
micro-architecture intel cpu-architecture optimization performance
Temporality of ST64B and MOVDIR64B
user_44803940
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4
1
161
micro-architecture arm64 x86-64 assembly cpu-architecture
how do i get the cpu information for my computer i.e functional units/latency etc
user_152331080
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3
1
203
micro-architecture x86 assembly cpu-architecture
Why does a loop transitioning from having its uops fed by the Uop Cache to LSD cause a spike in branch-misses?
user_113221310
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4
2
272
micro-architecture branch-prediction x86-64 micro-optimization cpu-architecture
Why does FADDP D-form have higher throughput than FADDP Q-form on the Cortex-A72
user_30182430
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2
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188
micro-architecture arm64 neon simd cpu-architecture
In which conditions the L1 IP-based stride prefetcher will be triggered?
user_152562550
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194
micro-architecture prefetch cpu-cache intel x86
What are the "long" and "short" scoreboards w.r.t. MIO/L1TEX?
user_15930770
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5
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1760
nsight-compute micro-architecture gpgpu cuda gpu
How does Load Store Queue work in the presence of MSHR?
user_149485660
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2
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359
micro-architecture cpu-cache cpu-architecture queue
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