I am currently learning basics computer architecture and I am working on implementing a FLAGS register that handles external interrupts. Supposedly the output of the register is connected to the controller to handle which instruction to execute upon the interrupt. Based on the output signals, the output shows conflicting signals when driving the signals to the controller. I presume this is because of the concurrent processes between the external interrupt driving signals to flag_data(3) interrupt flag and flag_out <= flag_reg process, but I'm not quite sure how I can improve this. My question is, what am I doing wrong here and how can I fix the implementation provided below?
To provide more context, once the interrupt happens at execute cycle (at 50ns) the controller supposedly sets the carry flag to 1 which is supposed to be flag_data(0). Signals are level triggered where controller and datapath operations happen at the falling and rising edges of the clock, respectively. At this part of the computer cycle, the external interrupt only manipulates the MSB and LSB of the flag signals (interrupt and carry flags). Also, Lf pin is used on updating the flag_reg signals while the new flag output is provided at rising edge considering it to only drive new signals during datapath execution (rising edge of the clock).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flags is
Port (
clk : in STD_LOGIC;
i : in STD_LOGIC; --interrupt pin
Lf : in STD_LOGIC; -- update flags register
flag_in : in STD_LOGIC_VECTOR (3 downto 0); -- input from ALU
flag_out : out STD_LOGIC_VECTOR (3 downto 0)); -- output to controller
end flags;
architecture Behavioral of flags is
signal flag_reg : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
begin
flag_reg <= flag_in when Lf = '1';
process(clk, i) is
begin
flag_reg(3) <= i;
if rising_edge(clk) then flag_out <= flag_reg; end if;
end process;
end Behavioral;
