cpu-architecture

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Do store instructions block subsequent instructions on a cache miss?
user_55016750
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5
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212
cpu-cache x86 concurrency cpu-architecture c++
Why doesn't RFO after retirement break memory ordering?
user_89903290
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5
1
334
rfo x86-64 cpu-cache assembly cpu-architecture
Execute operations of the same instruction separately in an OoO processor
user_137279120
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3
1
97
micro-architecture instructions x86 assembly cpu-architecture
Should combining memory fence for mutex acquire-exchange loop (or queue acquire-load loop) be done or should it be avoided?
user_29450270
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2
2
1518
memory-barriers arm micro-optimization cpu-architecture
Intel JCC Erratum - should JCC really be treated separately?
user_29450270
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3
1
610
micro-architecture intel x86 assembly cpu-architecture
Why are Docker multi-architecture needed (instead of the Docker Engine abstracting the differences)
user_17179790
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6
2
379
docker-engine docker-image docker cpu-architecture
MIPS Pipeline Stalls: SW after LW
user_55249760
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2
1
1936
mips forwarding pipeline cpu-architecture
What cache coherence solution do modern x86 CPUs use?
user_136521900
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6
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1031
mesi computer-science cpu-cache x86 cpu-architecture
Why is ONE basic arithmetic operation in for loop body executed SLOWER THAN TWO arithmetic operations?
user_53579860
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15
5
1125
google-benchmark assembly cpu-architecture c++ performance
Can the simple decoders in recent Intel microarchitectures handle all 1-µop instructions?
user_104619730
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5
1
449
x86-64 intel x86 cpu-architecture cpu
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