cpu-architecture

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RISC-V instruction to write dirty cache line to next level of cache
user_60902260
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2
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633
persistent-memory riscv instructions assembly cpu-architecture
Why is __int128_t faster than long long on x86-64 GCC?
user_129869290
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43
2
4834
integer-division x86-64 cpu-architecture c++ performance
Why does C# System.Decimal (decimal) "waste" bits?
user_15254250
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11
2
415
internals decimal data-structures cpu-architecture c#
How to count number of executed instructions of a process id including child processes
user_1695450
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5
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242
perf docker cpu-architecture linux performance
Determine Rank and Channel Bits in Haswell Physical Address Space
user_66610260
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2
0
76
chipset mapping intel reverse-engineering cpu-architecture
How does a CPU timer work if the count value is larger than what it can hold?
user_138420690
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2
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211
timer cpu-architecture linux c
why we can't move a 64-bit immediate value to memory?
user_96234010
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5
2
4856
immediate-operand x86-64 instruction-set assembly cpu-architecture
What happens for a RIP-relative load next to the current instruction? Cache hit?
user_100905580
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2
1
91
x86-64 cpu-cache x86 assembly cpu-architecture
Reducing bus traffic for cache line invalidation
user_458430
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7
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205
memory-barriers memory-model cpu-cache cpu-architecture multithreading
How do modern Intel x86 CPUs implement the total order over stores
user_22457070
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3
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1516
mesi memory-barriers intel x86 cpu-architecture
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