MIPS Pipeline Stalls: SW after LW

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I am confused as to how a Store Word Instruction coming after an LW using the same $rt causes a pipeline stall in MIPS. Consider this block of code:

  lw $s0,  0($t0)
  sw $s0, 12($t0)
  lw $s1,  4($t0)
  sw $s1, 16($t0)
  lw $s2,  8($t0)
  sw $s2, 20($t0)

Here 3 words are being shifted around in memory. For e.g in the first 2 lines, $s0 is loaded into , and then its contents are saved back in the memory. I'm not sure if the sw instruction required $s0 in EX stage or in MEM stage. if it is needed in MEM stage, wouldn't it be resolved just by forwarding without needing to stall the pipeline?

mips forwarding pipeline cpu-architecture
1 Answers

Hypothetically, yes. Forwarding into the MEM stage directly would make it possible to execute dependent LW and SW back-to-back. As long as the loaded word is stored by the SW at least. It wouldn't be possible to have the SW use that loaded word as the base of the address without a pipeline bubble, otherwise it would require forwarding back in time.

But typically you would see a pipeline such as below (source: a model of a 5 stage pipelined MIPS in SIM-PL), with only one forwarder which feeds into EX. With a setup like that, there is no way to forward from LW into SW, the hardware required for it isn't there.

MIPS pipeline

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