cpu-architecture

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How can memory destination BTS be significantly slower than load / BTS reg,reg / store?
user_113221310
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175
microcoding x86-64 assembly cpu-architecture performance
Slowing down CPU Frequency by imposing memory stress
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2
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962
intel cpu-architecture cpu linux c++
Little Endian vs. Big Endian architectures
user_119697430
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2
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727
data-representation endianness memory cpu-architecture
Travis thinks the architecture is 32-bit, but Python disagrees
user_30196890
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2
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61
travis-ci cpu-architecture python
Any reason to use BX R over MOV pc, R except thumb interwork pre ARMv7?
user_9041480
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10
1
952
micro-architecture branch-prediction arm assembly cpu-architecture
Bottleneck when using indexed addressing modes
user_104619730
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3
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172
addressing-mode x86-64 micro-optimization intel cpu-architecture
Cortex M4 LDR/STR timing
user_33739670
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5
2
680
cortex-m arm assembly cpu-architecture performance
Width of bus betwen cpu cache and cpu
user_122920000
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2
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562
amd-processor cpu-cache x86 cpu-architecture cpu
CPUs with instructions with more than two branch destinations
user_62630410
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3
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61
instruction-set cpu-architecture
How does a stack stores values in it?
user_63527720
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4
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549
callstack assembly stack cpu-architecture javascript
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