cpu-architecture

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How do the store buffer and Line Fill Buffer interact with each other?
user_5820100
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7
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2997
cpu-mds micro-architecture cpu-cache x86 cpu-architecture
When use write-through cache policy for pages
user_5820100
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3
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1438
page-tables cpu-cache x86 linux-kernel cpu-architecture
MIPS Jump instruction encoding: why left shifted, and why keep the high 4 bits of PC?
user_89812840
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2
1
1872
mips machine-code assembly cpu-architecture
32-byte aligned routine does not fit the uops cache
user_27861560
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7
2
742
intel x86 assembly cpu-architecture performance
What do multiple values or ranges means as the latency for a single instruction?
user_122025360
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2
1
159
micro-optimization x86 assembly cpu-architecture performance
Why use push/pop instead of sub and mov?
user_39685750
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4
1
1097
x86-64 micro-optimization x86 assembly cpu-architecture
Counting number of allocations into the Write Pending Queue - unexpected low result on NV memory
user_105915150
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4
1
565
persistent-memory x86-64 intel memory cpu-architecture
How many instructions need to be killed on a miss-predict in a 6-stage scalar or superscalar MIPS?
user_115056660
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4
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139
mips32 mips branch-prediction pipeline cpu-architecture
How to find the Number of physical CPU Cores (not logical SMT hyperthreads) via .NET Core?
user_130540170
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5
0
1189
.net-core hyperthreading cpu-architecture cpu .net
Why does adding an xorps instruction make this function using cvtsi2ss and addss ~5x faster?
user_6415070
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8
1
490
microbenchmark x86-64 clang sse cpu-architecture
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