chisel

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How does a missing boolean operator still compile?
user_21165850
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4
1
51
chisel scala
How to create a Vec literal from a Seq[Bool]
user_21165850
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3
1
105
chiseltest chisel
Developing Generic AXI4 Peripheral with Chisel
user_39551440
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2
1
163
rocket-chip chisel fpga
chisel Vec() in Bundle class cannot be implemented in Module class
user_180360040
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2
0
51
rocket-chip chisel
RegInit initializes value only on reset
user_71219060
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2
1
105
chisel scala
Chisel queue module test results don't match what i expected
user_172963070
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1
1
83
chiseltest chisel
In chisel, How to generate serval Module with different parameter?
user_177582380
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2
1
32
rocket-chip chisel scala
What does `vec type 'AnonymousBundle(IO io in <module>)' must be a Chisel type, not hardware` mean?
user_52044700
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1
1
91
chisel hdl module
Does chisel3's printf generate terminal output when simulating the emitted verilog?
user_165572440
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2
1
39
chisel
How to emitVerilog from Firrtl with annotations
user_176330620
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1
0
73
firrtl chisel verilog annotations
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