rocket-chip

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TIMESCALEMOD verilator error when attempting to add a new black box in chisel
user_196369430
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1
0
34
verilator rocket-chip chisel scala
How to find the number of PLIC contexts?
user_6486580
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8
1
99
riscv32 rocket-chip chisel
How to assign data to a register in chisel?
user_191796970
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1
1
36
rocket-chip riscv chisel
Implementing a diplomatic AXI Stream interface in Chisel - BundleMap.cloneType error
user_51770690
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2
1
157
rocket-chip chisel
Adding an MMIO peripheral to Rocket-chip as a submodule
user_89296850
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1
1
203
rocket-chip riscv chisel
Developing Generic AXI4 Peripheral with Chisel
user_39551440
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2
1
163
rocket-chip chisel fpga
chisel Vec() in Bundle class cannot be implemented in Module class
user_180360040
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2
0
51
rocket-chip chisel
In chisel, How to generate serval Module with different parameter?
user_177582380
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2
1
32
rocket-chip chisel scala
What are these `a.bits.user.amba_prot` signals and why are they only uninitialized conditionally in my HarnessBinder?
user_165572440
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1
1
135
rocket-chip chisel
Unrecognized opcode in creating custom RISC-V instruction
user_132897020
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1
0
445
riscv32 rocket-chip riscv
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