chisel

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Testing Chisel object functions that use hardware constructs
user_21165850
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2
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74
chiseltest chisel
Chisel invert Vec[Bool] one-liner
user_21165850
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3
2
89
chisel
How to understand the beat in chisel language?
user_149662270
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1
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94
riscv chisel cpu scala
What are these `a.bits.user.amba_prot` signals and why are they only uninitialized conditionally in my HarnessBinder?
user_165572440
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1
1
135
rocket-chip chisel
Why do poked values change on last clock cycle in chiseltest, thus failing asserts?
user_57092870
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2
1
52
chiseltest chisel
Create a generic Bundle in Chisel3
user_168217150
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2
1
164
chisel
How to add elements in Vec like a binary tree's leaf nodes?
user_56867150
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2
2
46
chisel
How to generate verilog code like "reg[n-1:0] = 90" with chisel3?
user_137184810
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2
1
128
chisel
Why Bool(true) != Bool(true) in chisel3?
user_44229570
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3
2
348
chiseltest chisel scala
What the purpose of `initSource`, `initSink` or `setSinkClock` in chiseltest test harness?
user_44229570
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1
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51
chiseltest chisel scala
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