firrtl

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how to get a critical path / bottleneck analysis of FIRRTL code?
user_1247040
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2
1
54
riscv firrtl chisel
what do "cmem", "infer", and "mport" mean?
user_1247040
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2
1
52
firrtl chisel
False "Combinational loop detected"
user_185348740
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2
1
179
firrtl chisel scala
Bundle using Mux
user_183519270
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1
1
42
firrtl chisel
How to emitVerilog from Firrtl with annotations
user_176330620
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1
0
73
firrtl chisel verilog annotations
Differences between LazyModule and LazyModuleImp
user_125122930
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1
1
201
rocket-chip riscv firrtl chisel
Chisel/FIRRTL DefnameDifferentPortsException
user_84097030
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3
1
130
firrtl chisel
How to convert a deprecated low Firrtl Transform to the Dependency API
user_3090390
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2
1
42
firrtl chisel
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