I am new to Chisel/Firrtl but I find it very interesting! I am looking for an example of how to take some annotation (like for example one-hot signal) from chisel3 through firrtl onto Verilog where it could be added as a comment.
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I am new to Chisel/Firrtl but I find it very interesting! I am looking for an example of how to take some annotation (like for example one-hot signal) from chisel3 through firrtl onto Verilog where it could be added as a comment.