The following line of code val mod_subexp_array = Vec(9, Module(new SubTaylor(fepar)).io) produces the following error:
chisel3.package$ExpectedChiselTypeException: vec type 'AnonymousBundle(IO io in SubTaylor)' must be a Chisel type, not hardware
The module SubTaylor is a module I've written, and I interface with it via an IO port. My objective is to create 9 instances of these SubTaylor modules and chain them together using their IOs. To resolve the problem above, I thought perhaps the SubTaylor module needed to be wrapped within a Wire:
val mod_subexp_array = Vec(9, Wire(Module(new SubTaylor(fepar))).io)
However, the errors message changed to wire type 'AnonymousBundle(IO io in SubTaylor)' must be a Chisel type, not hardware. As I currently understand, there are two different Wire datatypes. One wire datatype is a Chisel type, and the other is a hardware type. Is my understanding correct? And how am I supposed to define Vector as a Chisel type?