vivado

29 Questions
Newest Active Unanswered Frequent
Score
View
Card Compact
Logical equality for two different vector widths
user_77798690
•
1
1
348
vivado system-verilog
TCL processing arguments template, why [set argv {}]
user_125122930
•
1
1
79
synopsys-vcs vivado tcl shell bash
Concurrent assignment to a non-net '_' is not permitted
user_174761730
•
2
1
1157
vivado verilog
Register file not reading any data
user_134056070
•
2
1
67
vivado verilog
UART Transmit and receive data does not start (Vivado)
user_116567750
•
2
1
130
uart vivado verilog
Verilog inout port assignment results in X
user_115653640
•
1
1
252
vivado verilog
How to connect the inout data ports to multiple IOs
user_147069250
•
1
1
44
vivado fpga
How to represent 45 degree and 26.565 degree angle in 32 bit binary form?
user_114142270
•
2
1
151
cordic vivado system-verilog verilog fft
Why shouldn't I be using 'inout' rather than 'in' or 'out'?
user_147196790
•
2
1
408
vivado fpga vhdl
Why can't I use anything but (0 and 1) when I specify the radix in a literal?
user_83245850
•
2
0
62
vivado vhdl
Hot Questions