Concurrent assignment to a non-net '_' is not permitted

user_17476173 0
Viewed 1157

I'm getting the error:

concurrent assignment to a non-net 'A' is not permitted
concurrent assignment to a non-net 'B' is not permitted 
Static elaboration of top level Verilog design unit(s) in library work failed.

What am I doing wrong?

module ex1( input reg [1:0] a,
  input reg [1:0]b,
  output wire c,
  );
  assign c=(a>b)?(a=1'b1):(c=1'b0);     
endmodule 

module testbench(
    );
    reg[1:0]a=2'b11;
    reg [1:0]b=2'b00;
    wire c;
    always#10
    begin
      a=a-2'b01;
      b=b-2'b01;
    end
    initial
      #150 $finish;
    ex1 testbench2 (.a(a),
      .b(b),.c(c));
endmodule
vivado verilog
1 Answers

I get 3 syntax errors in your ex1 module.

The trailing comma in a port list is illegal. Change:

output wire c,

to:

output wire c

It is illegal to assign a value to an input port inside a module. This is illegal: a=1'b1. Assuming it was a typo to use a there, and you really meant to type c, you should change:

assign c=(a>b)?(a=1'b1):(c=1'b0);

to:

assign c = (a>b) ? 1'b1 : 1'b0;

You typically never want to make an assignment inside a conditional operator like your code does.

One simulator also complains about declaring an input port as a reg type. You should omit reg for a and b. Here is the recoded module:

module ex1 (
    input [1:0] a,
    input [1:0] b,
    output wire c
);
    assign c = (a>b) ? 1'b1 : 1'b0;     
endmodule
user_1977580
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