Logical equality for two different vector widths

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Why does logical equality for two vectors of different widths have an output like below?

module eq_test;

logic check;
logic [3:0] cmp_0;
logic       cmp_1 = 1'b0;

initial begin
    for (int i = 0; i < 16; i++) begin
        cmp_0 = i;
        check = (cmp_0 == cmp_1);
        $display("%b == %b is %b", cmp_0, cmp_1, check);
    end
end

endmodule

With Vivado Simulator

0000 == 0 is 1
0001 == 0 is 0
0010 == 0 is 0
0011 == 0 is 0
0100 == 0 is 0
0101 == 0 is 0
0110 == 0 is 0
0111 == 0 is 0
1000 == 0 is 0
1001 == 0 is 0
1010 == 0 is 0
1011 == 0 is 0
1100 == 0 is 0
1101 == 0 is 0
1110 == 0 is 0
1111 == 0 is 0

I can assume that the variable with smaller width cmp_1 is expanded (unsigned expand) to the larger variable width cmp_0, is that so?

vivado system-verilog
1 Answers

Yes, the variable with smaller width is expanded to the larger variable width.

This is described in IEEE Std 1800-2017, section 11.6.1 Rules for expression bit lengths.

The number of bits of an expression (known as the size of the expression) shall be determined by the operands involved in the expression and the context in which the expression is given.

In Table 11-21, the == operator has this comment:

Operands are sized to max(L(i),L(j))

where i and j represent expressions of an operand, and L(i) represents the bit length of the operand represented by i.

This is true for all simulators, not just for Vivado.

user_1977580
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