I am working on an SPI Master using ArtyA7 development board, and I'm wondering if it's possible to connect the inout data ports to multiple IOs which will be connected to multiple spi slaves ? I tried doing this :
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports spi_clk]
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports {spi_cs[0]}]
set_property -dict {PACKAGE_PIN k17 IOSTANDARD LVCMOS33} [get_ports {spi[0]}]
set_property -dict {PACKAGE_PIN k18 IOSTANDARD LVCMOS33} [get_ports {spi[1]}]
#JA
set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports {spi_cs[1]}]
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {spi[0]}]
set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {spi[1]}]
set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports spi_clk]
Where spi[i] is an inout port. But when I open the implemented design, I see that vivado implemented only the last constraints. What's wrong in my flow ?
