cpu-architecture

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Why does the latency of the sqrtsd instruction change based on the input? Intel processors
user_59273330
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1063
intel assembly cpu-architecture c performance
How is it possible for these 2 functions, executed in parallel, to output an unlikely result?
user_86342650
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3
3
90
concurrency assembly cpu-architecture
Why is LOCK a full barrier on x86?
user_13321710
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6
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741
memory-barriers x86 cpu-architecture
The reason behind back-off strategy for spin lock
user_27861560
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5
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617
compare-and-swap lock-free assembly cpu-architecture c++
Long latency instruction
user_1491380
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3
2
387
microbenchmark micro-optimization x86 cpu-architecture optimization
Why can _mm_pause() significantly improve performance?
user_5083430
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7
0
1905
lockless x86 assembly cpu-architecture performance
Do FP and integer division compete for the same throughput resources on x86 CPUs?
user_2241320
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7
1
435
intel x86 assembly cpu-architecture performance
How many ways-superscalar are modern Intel processors?
user_58107470
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5
1
1898
micro-architecture intel x86 cpu-architecture
Do any microprocessors today use Scoreboarding or Tomasulo's algorithm?
user_88519980
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2
2
698
processors hardware cpu-architecture
Is C++ considered a Von Neumann programming language?
user_23526710
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7
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2109
von-neumann computer-science language-design cpu-architecture c++
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