cpu-architecture

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gcc: Differences between -march=native and -march=<specific arch>
user_9552730
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2
0
1016
compiler-optimization cpu-architecture gcc
How to explain poor performance on Xeon processors for a loop with both sequential copy and a scattered store?
user_142344440
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14
1
649
amd-processor cpu-cache intel cpu-architecture performance
Does clwb take care of the write in store buffer?
user_60902260
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3
2
163
persistent-memory x86-64 x86 assembly cpu-architecture
What is the granularity of "masked" stores in AVX512?
user_20598930
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8
1
179
avx512 intel assembly cpu-architecture performance
Intuition for implementing logic gates
user_141054190
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2
2
261
nand2tetris logical-operators cpu-architecture
Is a "single cycle cpu" possible if asynchronous components are used?
user_20304110
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2
2
478
retro-computing mips hardware cpu-architecture cpu
Why doesn't mov set the zero flag?
user_122831680
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3
0
642
eflags x86 assembly cpu-architecture
Is there any reason not to remove checks for the Pentium FDIV bug?
user_31954770
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5
0
210
compiler-optimization vb6 x86 cpu-architecture
Data Hazards and stalls
user_62382750
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4
2
367
mips assembly cpu-architecture
How to tell if there is fault in the truth table?
user_136268740
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3
2
335
truthtable boolean-algebra boolean-expression boolean-logic cpu-architecture
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