Width of bus betwen cpu cache and cpu

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enter image description here I can't figure out the width of bus between cpu and cpu cache in modern PC's. I didn't find anything reliable in the internet. All what I have is a block diagram for Zen (AMD) microarchitecture, which says that, L1 and L2 caches can transfer 32B(256b) per single cycle. I'm guessing the bus width is 256 lines (assuming single data rate). But, there are double data rate transfers, like between memory controller and DDR memory.

Summarizing:

  1. Is the bus width between cpu and cpu cache 256 lines?
  2. If yes, does that means, that read entire cache line from L1 requires two cpu cycles?
amd-processor cpu-cache x86 cpu-architecture cpu
1 Answers

This kind of information can be found in the optimization manuals from Intel and AMD, but usually in terms of port bandwdith, not exactly width, because that's what most people care about.

The L1D cache in the Zen microarchitecture has 16 banks and 3 128-bit ports, two of which can handle load-type requests and one can handle store-type requests. So the maximum core-L1D bandwdith is 128*3 bits per cycle. In Zen 2, the ports were expanded to 256 bits/c each and the number of banks was cut by half. So the maximum core-L1D bandwdith in Zen 2 is 256*3 bits per cycle, but the chance of achieving max bandwdith is lower.

Consider Ice Lake as an example from Intel processors. The L1D cache has 4 ports, two 512-bit loads and two 256-bit stores. The store ports can either handle a single 512-bit store request per two cycles or two 256-bit store requests per cycle but only if the two stores are fully contained within the same cache line and have the same memory type. It appears to me that these two store ports are implemented actually as a single 256-bit wide store port with dual store merging capability. So the total number of true ports from the core side seems to be 3.

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