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cpu-architecture
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Where system stores 16 segment addresses while segment registers are 4?
user_19812695
0
•
asked Aug 21, 2022
1
1
47
x86-16
memory-segmentation
cpu-registers
assembly
cpu-architecture
How to handle branch mispredictions that seem to depend on machine code position?
user_9611473
0
•
asked Aug 20, 2022
7
1
152
branch-prediction
benchmarking
cpu-architecture
c++
performance
Multicopy atomicity vs Cache Coherence
user_8521177
0
•
asked Aug 20, 2022
1
1
69
memory-model
atomic
cpu-cache
cpu-architecture
caching
Why can't we have a safe ISA?
user_13784274
0
•
asked Aug 15, 2022
2
2
61
memory-safety
instruction-set
cpu-architecture
memory-management
security
Can hardware threads access main memory at the same time?
user_10662977
0
•
asked Aug 13, 2022
1
1
73
memory-bandwidth
hyperthreading
x86
memory
cpu-architecture
How is the instruction memory initialized?
user_10916973
0
•
asked Aug 12, 2022
1
1
64
boot
bootloader
reset
cpu-architecture
cpu
Performance of AVX-512 masked memory accesses
user_459150
0
•
asked Aug 10, 2022
10
1
221
avx512
x86
cpu-architecture
performance
Why are far pointers slow?
user_299434
0
•
asked Jul 28, 2022
2
1
72
x86-16
memory-segmentation
dos
cpu-architecture
performance
Is uops.info wrong about vinserti128?
user_3154996
0
•
asked Jul 25, 2022
4
1
85
avx2
simd
x86
assembly
cpu-architecture
Running two functions at the exact same time on multiple cores
user_11875437
0
•
asked Jul 23, 2022
2
2
82
operating-system
multicore
cpu-architecture
pthreads
c
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