Performance of AVX-512 masked memory accesses

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Can masking improve the performance of AVX-512 memory operations (load/store/gather/scatter and non-shuffling load-ops)?

Seeing as masked out elements don't trigger memory faults, one would assume that masking helps performance in those cases, however, what about the following if a 0 mask was used:

  • a load/store which crosses a cacheline boundary - would this suppress the cacheline cross penalty?
    • and suppress a load from L2 cache (or further away) if either or both cachelines aren't in L1?
    • does as masked out load affect memory reordering?
  • gather/scatter throughput seems to be limited by the CPU's load-store unit, but would masking off elements lessen the impact of this?

This would be in the context of current Intel processors at the moment, but would be interesting to see how an AVX-512 enabled AMD processor handles this.

avx512 x86 cpu-architecture performance
1 Answers

I tried running some tests on an AVX-512 enabled Intel 12700K. I haven't done this before, so wouldn't be surprised if I messed something up.

I'm not sure how to test for L2 behaviour or reordering reliably, but for the rest, I took nanoBench and ran this script, yielding these results (CSV form).

Instructions tested:

  • Load
    • VMOVDQU8/64
    • VPADDB/Q (load-op)
    • VPEXPANDB/Q
    • VPMOVZXBD
  • Store
    • VMOVDQU8/64
    • VPCOMPRESSB/Q
    • VPMOVQW
  • VPGATHERDD & VPSCATTERDD

I can't see any difference based on mask value (0 or -1 tested) for loads, however there may be a slight difference for stores. Not entirely sure what CORE_CYCLES means, but it's one cycle less for the 0 mask compared to a -1 mask.
This behaviour seems consistent across the store instructions tested, with the load+store test of VMOVDQU64 being the odd exception (difference of ~5 cycles). I'm not sure why, but result is repeatable. Cacheline crossing doesn't appear to be reason behind the difference either - testing masks such as 1, 2 and 128 seem to indicate that lower CORE_CYCLES can only be achieved with a 0 mask.

Gather/scatter is giving me identical results regardless of the mask or the number of cachelines the instruction would hit.

I think it's fair to assume that the mask value generally doesn't affect masked memory access (beyond perhaps suppressing faults). Maybe it has a minor impact on stores, but am unclear about this and could be uArch dependent.

user_4591500
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