cpu-architecture

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Use "arithmetic shift right" as "less than zero"
user_119208920
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53
avx avx2 sse floating-point cpu-architecture
Why A and B registers are used in multicycle Datapath?
user_141046210
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1
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52
spim mips cpu-registers cpu-architecture
Explanation for why effective DRAM bandwidth reduces upon adding CPUs
user_72515880
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3
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153
numa parallel-processing intel cpu-architecture performance
Why didn't x86 implement direct core-to-core messaging assembly/cpu instructions?
user_14700920
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5
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166
message-passing intel x86 assembly cpu-architecture
C++ atomics and memory_order with RDMA
user_5389550
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4
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207
rdma stdatomic memory-barriers cpu-architecture c++
Performance differ significantly when inner loop iterates less times?
user_141809730
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6
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194
x86-64 assembly cpu-architecture gcc c++
How to determine machine architecture in Python?
user_189109670
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2
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168
cpu-architecture python
Does sequential consistency implies cache coherence?
user_147136540
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2
2
78
consistency distributed-system concurrency cpu-architecture caching
8086 lock pin and ASM LOCK prefix how it works
user_131607060
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2
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112
x86-16 atomic assembly cpu-architecture locking
What happens to outstanding stores after an object is deleted?
user_11651360
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172
memory-barriers x86 cpu-architecture multithreading c++
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