cpu-architecture

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Can all of L2/L3 cache be used by data? If so, why does the Graviton 3 bandwidth plot drop off after half the L2/L3 size, but only gradually?
user_19371970
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96
memory-bandwidth arm64 cpu-cache cpu-architecture performance
Memory throughput for strided memory accesses
user_2955020
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2
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55
gather memory-bandwidth x86-64 cpu-architecture
c++11: how to produce "spurious failures" upon compare_exchange_weak?
user_61641720
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5
1
96
compare-exchange-weak compare-exchange-strong stdatomic cpu-architecture c++
If a function was entered via a near call, can it do a far tail call without breaking return address prediction?
user_75090650
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5
0
109
branch-prediction x86-64 x86 assembly cpu-architecture
Is there a special benefit to consuming whole cache lines between iterations of a loop?
user_82179190
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10
0
129
simd cpu-cache cpu-architecture visual-c++ c++
Some confusing concepts about cache and memory
user_188224750
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1
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23
memory cpu-architecture caching
Why does MOVD/MOVQ between GP and SIMD registers have quite high latency?
user_176658070
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3
1
113
simd sse x86 assembly cpu-architecture
Unaligned access performance on Intel x86 vs AMD x86 CPUs
user_16256890
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3
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149
amd-processor x86-64 memory-alignment intel cpu-architecture
Why does bfloat16 have so many exponent bits?
user_458430
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4
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138
half-precision-float machine-learning neural-network floating-point cpu-architecture
Does RSQRTSS break the dependency on the destination register?
user_176658070
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4
1
93
sse x86 assembly cpu-architecture
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