cpu-architecture

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Bubble sort slower with -O3 than -O2 with GCC
user_171107860
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147
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31143
compiler-optimization x86-64 cpu-architecture gcc c
When source registers in avx instruction can be reused
user_30129290
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3
2
202
avx micro-optimization simd assembly cpu-architecture
What's the point of having a virtual address that's larger than the effective address?
user_12273530
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5
1
204
powerpc virtual-memory cpu-architecture
How can I determine the size of words in bits (32 or 64) on the architecture?
user_109213430
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2
1
199
go 32bit-64bit cpu-architecture
Which sequence of instructions has better performance for zeroing one register or another?
user_36704730
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3
2
146
mips micro-optimization assembly cpu-architecture performance
How does perf record (or other profilers) pick which instruction to count as costing time?
user_22398720
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4
1
247
perf assembly cpu-architecture performance
Why does L2 hardware prefetcher perform worse with only 1 KiB or 2 KiB access size?
user_113380060
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2
1
190
prefetch intel x86 cpu-architecture performance
Masked and unmasked FP exceptions in the same instruction: are all bits set in MXCSR before handling the unmasked exception?
user_162422780
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2
0
142
floating-point-exceptions x86-64 sse assembly cpu-architecture
What Are Conflict Misses Exactly?
user_164657390
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2
1
671
cpu-cache cpu-architecture caching
Finding maximum number of register counts from instruction size, op-code size, and number of operands
user_169230950
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2
1
321
instruction-set computer-science cpu-registers cpu-architecture
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