Recently, I found out that actually perf (or pprof) may show in disassembly view instruction timing near the line that didn't actually take this time. The real instruction, which actually took this time, is before it. I know a vague explanation that this happens due to instruction pipelining in CPU. However, I would like to find out the following:
- Is there a more detailed explanation of this effect?
- Is it documented in perf or pprof? I haven't found any references.
- Is there a way to obtain correctly placed timings?