cpu-architecture

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Why does the short (16-bit) variable mov a value to a register and store that, unlike other widths?
user_138193730
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5
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122
micro-optimization x86 assembly cpu-architecture c
Why does "INT_MAX * INT_MAX" product give 1?
user_78501480
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2
2
147
integer-overflow cpu-architecture c
Do I need to externally call flush if using cuda api to copy from GPU Memory to Persistent Memory?
user_16588390
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2
2
103
clflush persistent-memory flush cuda cpu-architecture
How does a CPU handle asynchronous interrupts?
user_117409090
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2
1
137
interrupt arm x86 cpu-architecture
Temporality of ST64B and MOVDIR64B
user_44803940
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4
1
161
micro-architecture arm64 x86-64 assembly cpu-architecture
Assembly why is "lea eax, [eax + eax*const]; shl eax, eax, const;" combined faster than "imul eax, eax, const" according to gcc -O2?
user_128929370
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6
2
392
x86-64 assembly cpu-architecture optimization c
What does M1 mac optimization process for an application mean?
user_161630440
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3
1
286
apple-m1 cpu-architecture cpu macos
The strong-ness of x86 store instruction wrt. SC-DRF?
user_44851680
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2
1
230
stdatomic memory-barriers memory-model cpu-architecture c++
Intel JCC Erratum - what is the effect of prefixes used for mitigation?
user_29450270
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5
1
208
micro-optimization intel x86 assembly cpu-architecture
Does an OS choose a memory controller when allocating memory in a server with multiple controllers? How?
user_11651360
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2
2
96
ram x86 cpu-architecture memory-management linux
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