Can't compile with VHDL 2008 Quartus Prime

user_14900893 0
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I'm using Quartus Prime Lite Edition and I want to use unary operator nand on std_logic_vector like this

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity example1 is
    port( 
        BIN : in std_logic_vector (7 downto 0);
        result : out std_logic
    );
end;

architecture Beh of example1 is
begin
    
    result <= nand BIN;
        
end Beh;

I tried to follow this instructions, changed VHDL version under VHDL Input in Compiler Settings. Still no effect and getting: Error (10500): VHDL syntax error at lab2.vhd(16) near text "nand"; expecting "(", or an identifier ("nand" is a reserved keyword), or unary operator

quartus vhdl intel
2 Answers
user_149008930

This error is coming as "nand" requires two inputs.

From your question, it appears to me that you want to perform the bitwise nand operation on the input.

If yes, you can replace architecture as follows. I am assuming that you are familiar with the "generate for" syntax!

architecture Beh of example1 is 
--Signals for Storing Intermediate Bitwise Values
signal temp1:std_logic_vector(3 downto 0);
signal temp2:std_logic_vector(1 downto 0);

begin
-- First level of NAND Operations

label_1: for i in 0 to 3 generate
temp1(i)<=BIN(2*i) nand BIN(2*i+1);
end generate label_1;

-- Second level of NAND Operations

label_2: for j in 0 to 1 generate
temp2(j)<= temp1(2*j) nand temp1(2*j+1);
end generate label_2;

-- Getting the Final Output 

result<= temp2(1) nand temp2(0);
end Beh;

Thanks, Dr. Ray

user_157790120
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