intel-fpga

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port SYCL/DPC++ code originally written for GPUs to FPGAs
user_116549860
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84
dpc++ intel-oneapi intel-fpga sycl intel
Design of compression using OpenCL FPGA
user_112127140
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2
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87
intel-fpga opencl
Flashing a Cyclone IV's SROM chip via its JTAG connection
user_169408810
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1
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28
intel-fpga flashing fpga
In Intel Quartus, can I initialize RAM using a string parameter?
user_12875540
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2
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185
quartus intel-fpga system-verilog fpga verilog
how can i use printf in opencl correctly?
user_164229170
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1
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110
intel-fpga opencl c
Does Quartus support in-memory synthesis?
user_116576410
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1
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49
quartus intel-fpga
What am I doing wrong? Testbench not updating correctly
user_152040470
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1
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75
quartus intel-fpga fpga verilog
#address-cells and #size-cells field in device tree overlay range property
user_11592900
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2
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1894
intel-fpga device-tree fpga embedded-linux linux
How to fix libXft.so.2: cannot open shared object file when simulating hardware in Quartus 20.1 running on Pop_OS 20.04
user_138604460
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4
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8278
quartus intel-fpga ubuntu
Quartus does not allow using a Generate block in Verilog
user_50707330
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445
quartus intel-fpga fpga hdl verilog
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