hdl

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Is it possible to declare conditionnal signals in io bundle?
user_44229570
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2
1
55
chisel hdl scala
How to set a signal at both posedge and negedge of a clock?
user_139726560
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2
1
734
xilinx-ise hdl verilog
What is the difference between these 2 counters?
user_136887250
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2
2
97
system-verilog hdl verilog
How to define output Reg in Chisel properly
user_88023700
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2
1
561
register-transfer-level chisel hdl
How do I create a C/C++ preprocessor style macro in Chisel HDL?
user_53997340
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2
1
155
chisel hdl verilog macros scala
Quartus does not allow using a Generate block in Verilog
user_50707330
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2
2
445
quartus intel-fpga fpga hdl verilog
Simple VHDL testbench procedure for sending serial bytes?
user_43142040
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3
3
1309
fpga hdl vhdl
Is it possible to have a while loop in chisel based on a condition of Chisel data types?
user_81370840
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3
2
433
chisel hdl while-loop scala
What is the purpose of 'pure' keyword in the clash tutorial example?
user_44229570
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2
1
205
clash hdl haskell
Expression _GEN_7 is used as a FEMALE but can only be used as a MALE
user_115939070
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4
1
79
register-transfer-level chisel hdl scala
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