cpu-architecture

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Why is POP slow when using register R12?
user_104619730
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293
micro-optimization intel x86 cpu-architecture performance
Writeback of clean cache lines in Skylake?
user_78408700
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178
cpu-cache intel x86 cpu-architecture
Do cache block replacement policies in x86 prefer clean blocks over dirty blocks?
user_60902260
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2
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38
micro-architecture x86-64 cpu-cache cpu-architecture
Can you have torn reads/writes between two threads pinned to different processors, if the system is cache coherent?
user_144472960
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2
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243
atomic cpu-cache cpu-architecture multithreading
What is packed and unpacked and extended packed data
user_76442430
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1025
avx avx2 simd sse cpu-architecture
The execution process of the instruction and the realization in gem5?
user_143280980
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297
micro-architecture gem5 instructions x86 cpu-architecture
How can we expect a program to complete in order?
user_98044500
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65
microprocessors cpu-architecture cpu
How does trace-inputs provided to trace-driven simulators look like?
user_49722960
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25
branch-prediction simulator cpu-architecture trace memory-management
Way prediction in modern cache
user_49722960
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1875
micro-architecture cpu-cache processor cpu-architecture caching
Can a speculatively executed CPU branch contain opcodes that access RAM?
user_30232920
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1241
speculative-execution cpu-architecture cpu
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